3. Top-Level view of computer function and interconnection

Contemporary computer design based on von Neumann architecture

Key concepts of von Neumann architecture

  • Data and instruction are stored in a single read-only memory

  • Contents of the memory are addressable by location, without regard to the type of data contained there

  • Execution occurs in a sequential fashion from one instruction to the next (unless explicitly modified)

Hardwired Program

  • Result of the process of connecting the various components in the designed architecture

Programming in hardware

Data -> [Sequence of arithmetic and logic functions] -> Results

Programming in software

Instruction codes -> [Instruction interpreter] -> Control Signals -> [General-purpose arithmetic and logic functions]

Data -> [General-purpose arithmetic and logic functions] -> Results

Software and I/O Components

Software

  • A sequence of codes or instructions

  • Part of the hardware interprets each instruction and generate control signals

  • Provide a new sequence of codes for each new program instead of rewiring the hardware

Major components

  • CPU

    • Instruction Interpreter

    • The module of general-purpose arithmetic and logic functions

  • I/O Components

    • Input module

      • Contains basic components for accepting data and instructions and converting them into an internal form of signals usable by the system

    • Output module

      • Means of reporting results

Memory, MAR, and MBR

Memory Address Register - MAR

Specifies the address in memory for the next read or write

Memory Buffer Register - MBR

Contains the data to be written into memory or receives the data read from memory

I/O address register - I/O AR

Specifies a particular I/O device

I/O buffer register I/O BR

Used for the exchange of data between an I/O module and the CPU

Basic Instruction Cycle

Start -> Fetch Next Instruction -> Execute Instruction -> Halt

Fetch Cycle

  1. At beginning of each instruction cycle, the processor fetches an instruction from memory

  2. The program counter (PC) holds the address of the instruction to be fetched next

  3. The processor increments the PC after each instruction fetch so that it will fetch the next instruction in sequence

  4. The fetched instruction loaded into the Instruction Register (IR)

  5. The processor interprets the instruction and performs the required action

Instead of memory reference, an instruction may specify an I/O operation

Instruction Cycle Diagram

Action Categories

Processor-memory: Data transferred from processor to memory or from memory to processor

Processor-I/O: Data to or from a peripheral device by the processor and an I/O module

Data processing: The processor may perform some arithmetic or logic operation on data

Control: An Instruction may specify that the sequence of execution to be altered

Interrupt

All computers provide a mechanism by which other modules may interrupt the normal processing of the computer

Most common classes of interrupts: Program (exception), Timer, I/O, and Hardware Failure

  • Interrupts are provided primarily as a way to improve processing efficiency

  • Most external devices are much slower than the processor

  • The processor is transferring data to a printer using the instruction cycle

    • After the write operation, the processor must pause and remain idle

Instruction Cycle with Interrupt

  • When the external device becomes ready - the device sends an interrupt request signal to the processor: The processor responds by suspending the operation of the current program, branching off to a program to survive

  • The particular I/O device, known as an interrupt handler, and resuming the original execution after the device is serviced

  • An interrupt processing is: an interruption of the normal sequence of execution

Instruction Cycle with Interrupts

If interrupts occur, the processor does the following

  1. Suspend execution of the current program being executed and saves its context

  2. set the program counter to the starting address of an interrupt handler routine

  3. proceeds to the fetch cycle and fetch the first instruction in the interrupt handler program

Interrupt Handler Routine

  • Generally part of the operating system. Typically this program determines the nature of the interrupt and performs whatever actions are needed

  • e.g. The handler determines which I/O module generate the interrupt - will write more data out to that I/O module

  • When the interrupt handler routine is completed, the processor can resume execution of the user program at the point of interruption

Extra instructions must be executed (in the interrupt handler) to decide on the appropriate action

I/O Operation: Short I/O wait and Long I/O wait

Long I/O waitL the program reaches the second write call before the I/O operation spawned by the first call is complete

Instruction Cycle State Diagram, with Interrupts

Multiple Interrupts

  1. Disable interrupt

    1. When an interrupt occurs, interrupts are disabled immediately

    2. After the interrupt handler routine completes, interrupts are enabled before resuming the program, processor checks to see if additional interrupts have occurred

    3. Drawback: it does not take into account relative priority or time-critical needs

  2. Define priorities

    • for interrupts and allow an interrupt of higher priority

Interrupt Service Routine (ISR)

I/O Function

I/O module can exchange data directly with the processor

Processor can read data from or write data to an I/O module

  • Processor identifies a specified device that is controlled by a particular I/O module

  • I/O instructions rather than referencing instructions

Sometimes, I/O exchanges allowed to occur directly with memory

  • Processor grants to an I/O module thw authority to read from or write to memory so that the I/O memory transfer can occur without tying up the processor

  • The I/O module issues read or write commands to memory relieving the processor or responsibility for the exchange

  • known as direct memory access (DMA)

Computer Components

Memory:

  • a memory module consists of N words of equal length

  • every word assigned a unique numerical address

  • a word of data can be read from or written into the memory

  • location of operation specified by an address

I/O Module:

  • internal viewly, similar to memory

  • Two Operations

    • Read

    • Write

  • an I/O module may control more than one external devices

Processor

  • reads in instruction and data, writes out data after processing

  • uses control signals to control the overall operation of the system

  • receives interrupt signals

The interconnection structure must support the following types of transfers

Memory to Processor: Processor reads an instruction or a unit of data from memoey

Processor to Memory: Processor writes a unit of data to memory

I/O to Processor:

Processor to I/O

I/O to or from Memory

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