9. Pipeline *

$$r=max⁡[r_i ]+d ; 1≤ⅈ≤k$$

$$r=r_m+d$$

$$r_m≫d$$

$$r=r_m$$

$$r=max⁡[r_i ]+d$$

• r : cycle time of an instruction pipeline

• r_m : maximum stage delay/latency

• d : time delay/ latency of a latch (time needed to advance singnals and data from one stage to the next stage)

• k : number of stages in the instruction pipeline

• Total time (T_k) required to execute all n instructions (with no branch)

Total time required to execute all n instructions

$$T_k=[k+(n-1)]r$$

Speed up

$$𝑆_𝑘=𝑆𝑒𝑞𝑢𝑒𝑛𝑡𝑖𝑎𝑙 (𝑇𝑖𝑚𝑒) /𝑃𝑖𝑝𝑒𝑙𝑖𝑛𝑒 (𝑇𝑖𝑚𝑒)$$

$$=𝑛𝑘𝑟/[𝑘+(𝑛−1)]𝑟$$

$$=𝑛𝑘/𝑘+(𝑛−1)$$

Latency

Latency = Cycle time x No. of pipeline stages.

Given an unpipelined processor with 10ns cycle time and pipeline latches with 0.5ns latency, what are the cycle times of pipelined versions of the processor with 2, 4, 8, and 16 stages if the datapath logic is evenly divided among the pipeline stages? Also, what is the latency of each of the pipelined versions of processor?

stage	cycle time	latency
2	10/2+0.5 = 5.5ns	10+2*0.5=11ns
4	10/4+0.5 = 3ns	10+4*0.5=12ns
8	10/8+0.5=1.625ns	10+8*0.5=14ns
16	10/16+0.5=1.125ns	10+16*0.5=18ns